module IF_ID(
    input clk,
    input [4:0] NEXT_Rs,NEXT_Rt,NEXT_Rd,NEXT_shf,
    input [31:0]NEXT_pc,
    input [31:0]NEXT_bnpc,
    input [31:0]NEXT_ins,
    input [3:0] NEXT_ALUctr,
    input [2:0] NEXT_Branch,
    input [1:0] NEXT_Jump,
    input [1:0] NEXT_RegWr,
    input NEXT_RegDst,
    input NEXT_ExtOp,
    input NEXT_ALUsrc,
    input [1:0] NEXT_MemWr,
    input NEXT_MemtoReg,
    input NEXT_ALUshf,
    input NEXT_R31wr,
    output reg [31:0] pc,
    output reg [31:0] bnpc,
    output reg [31:0] ins,
    output reg [3:0] ALUctr,
    output reg [2:0] Branch,
    output reg [1:0] Jump,
    output reg [1:0] RegWr,
    output reg RegDst,
    output reg ExtOp,
    output reg ALUsrc,
    output reg [1:0] MemWr,
    output reg MemtoReg,
    output reg ALUshf,
    output reg R31wr
);


always @(posedge clk) begin
   ALUctr = NEXT_ALUctr;
   Branch = NEXT_Branch;
   Jump = NEXT_Jump;
   RegWr = NEXT_RegWr;
   RegDst = NEXT_RegDst;
   ExtOp = NEXT_ExtOp;
   ALUsrc = NEXT_ALUsrc;
   MemWr = NEXT_MemWr;
   MemtoReg = NEXT_MemtoReg;
   ALUshf = NEXT_ALUshf;
   R31wr = NEXT_R31wr; 
   pc = NEXT_pc;
   ins = NEXT_ins;
   bnpc = NEXT_bnpc;
end

endmodule // 